Critical path analysis is one of the most important stages of circuit design, in part, because it can help determine the speed at which a circuit may be run. As circuits are quickly becoming more complicated, critical path analysis, as with many other circuit analysis techniques, is becoming increasingly computerized for efficiency purposes.
Also, as circuits grow in complexity (sometimes reaching thousands and sometimes millions of gates), it is imperative to decrease the number of computer resources and hours spent on evaluating these designs. This is extremely important with respect to critical path analysis. Especially, in the current climate of competition, it is imperative that the speed of a circuit be determined before investing substantial amounts of money on making and marketing a device that may be dwarfed by solutions from competitors.
Accordingly, critical path analysis is not only a tool for engineers to determine if their circuit design works, but also a tool for a marketing and finance division of a company to determine whether a given circuit design is worthy of pursuing.
Generally, circuit designers use a software program, such as HSpice provided by Avant Corporation of Fremont, Calif., to simulate the critical path schematics for their designs. Since the logic gates have different delays through them for rising and falling output nodes, the critical path of a circuit would have to be simulated for both rising and falling edges of a final output node. This requires creating at least two different schematics and simulations to calculate these delays.
After running these simulations, the higher of the rising or falling delays represents the worst-case delay. And, the worst-case delay in turn defines the final delay of the circuit. The final delay indicates the maximum frequency at which a design may safely run. Accordingly, it is important to set up these simulations carefully and efficiently.